The invention relates to the general field of high power field effect transistors.
Power MOSFETs have been widely applied to a variety of power electronics systems because of their inherent advantages such as high speed, low on-resistance, and excellent thermal stability. One of the most efficient methods to reduce on-resistance is to increase the packing density and the vertical (trench gate) MOSFET has been acknowledged to be the best device structure for achieving this.
A conventional device structure and the process flow for its manufacture are shown in FIG. 1. Starting with FIG. 1a, after P body 13 is diffused into an N+ Nxe2x88x92 epitaxial wafer 11 and 12, thin SiO2 and Si3N4 films 14 and 15 respectively, are grown over the wafer. Rectangular trenches 116 are then formed by using RIE (reactive ion etching) followed by oxidation to form gate layer 114 (FIG. 1b). In-situ doped poly-Si 122 is then deposited to refill the trenches. After polysilicon etch back, the Si3N4 and SiO2 films are removed, as shown in FIG. 1c). Photolithography is then used to define the N+ source region 151 by means of photoresist maks 112, followed by the N+ source implantation 110 (FIG.1d).
Another photolithography step is used to form P body contact region 181. Finally, contact holes formation, through passivation layer 102, and Al-metalization (layer 101) are performed to complete device fabrication (FIG. 1e).
The only way to further increase device density is to decrease device pitch. For the conventional process described in FIGS. 1a-1e, the pitch is determined by the trench width, the N+ source width, and the P body contact width. Thus the pitch limit is set by the lithography technology. To reduce pitch still further implies a reduction of the design rules and this is a high cost approach.
Kim (see reference below) has proposed a self-aligned technique to reduce device pitch in which an oxide spacer is used as a hard mask to etch a trench. Because of the rounded corner of such as spacer, the trench profile is tapered so that the device pitch still exceeds 2 microns. The maximum device density is 110 Mcell/in2. Furthermore, the N+ region at the bottom of the trench will degrade the quality of gate oxide and result in a locally stronger electric field. Another drawback is the small contact area to the source.
The present invention discloses a fully self-aligned trench gate MOSFET technique which uses self-aligned source and drain contacts and also saves one photolithography step in the process. With this technique the device density can be greatly increased by altering photolithography process. An additional benefit of the technique is a lower gate resistance owing to silicidation at the gate.
A routine search of the prior art was performed with the following references of interest being found:
D. Ueda et al. xe2x80x9cAn ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned processxe2x80x9d IEEE Trans. El. Dev. vol. ED-34 no. 4, April 1987 pp. 926-930.
T. Syau et al. xe2x80x9cComparison of ultra-low specific on-resistance UMOSFET structures: The ACCUFET, EXTFET, INVFET, and conventional UMOSFETsxe2x80x9d IEEE Trans. El. Dev. vol. ED41 no. 5, May 1994 pp. 800-808.
B. J. Baliga xe2x80x9cTrends in power discrete devicesxe2x80x9d Proc. 1998 Intl. Symp. on power semiconductor devices and Icsxe2x80x9d pp. 2-10.
J. Kim et al. xe2x80x9cHigh-density low on-resistance trench MOSFETs employing oxide spacers and self-align technique for DC/DC Converterxe2x80x9d ISPSD""May 22-25, 2000 Toulouse, France, pp. 381-384.
U.S. Pat. No. 5,915,180 (Hara et al.) shows a vertical trench gate power MOSFET. U.S. Pat. No. 6,015,737 (Tokura et al.), U.S. Pat. No. 6,096,608 (Williams), U.S. 5,714,781 (Yamamoto et al., and U.S. Pat. No. 5,897,343 (Mathew et al.) all show other vertical power MOSFETs. In U.S. Pat. No. 6,137,135, Kubo et al. disclose a vertical trench MOSFET.
It has been an object of at least one embodiment of the present invention to provide a process for manufacturing a vertical power MOSFET.
Another object of at least one embodiment of the present invention has been that said process result in an MOSFET that has, relative to the prior art, higher cell density, higher speed, easy scalability, and wide application.
A further object of at least one embodiment of the present invention has been that said process be fully compatible with existing processes used for the manufacture of vertical power MOSFETs.
These objects have been achieved by means of a sidewall doping process that effectively reduces the source width, and hence the device pitch. This sidewall doping process also eliminates the need for a source implantation mask while the sidewall spacer facilitates silicide formation at the source, the P body contact, and the polysilicon gate simultaneously. Since the source and P body are fully covered by silicide, the contact number and contact resistance can be minimized. The silicided polysilicon gate has a low sheet resistance of about 4-6 ohm/square, resulting in a higher operating frequency.